The present invention relates to the field of electronic circuits, and, more particularly, to programmable logic devices.
Programmable logic devices, such as field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), include a plurality of memory elements/reconfigurable elements which store circuit information and control the programmable logic circuit""s operation. The reconfigurable elements in FPGAs/CPLDs are usually complementary metal oxide semiconductor (CMOS) latches. These latches store information/data bits that determine the lookup table logic, the routing information, and other details which are solely dependent on the circuit being implemented in the given device. As the number of these latches increases, it takes quite some time to configure the FPGA/CPLD for a given circuit implementation. The configuration data is generated by software tools that map, place, and route the input circuit netlist.
Typical prior art approaches implement the concept illustrated in FIG. 1. The configuration latches are connected as arrays of latches 11 with the write signal of the latches in rows 5 tied together. A shift register structure 1 is beside the latch array which enables the write signal of the latches in rows, one row at a time. The write activation bit 4 shifts across the array to activate the write signals in rows.
Another shift register 3 has a length equal to the number of columns in the latch array. The purpose of this register is to serially accept a data frame to be loaded into a particular row of the latch array. The length of this register may vary depending on any error correction or parity check circuits which may be incorporated in the device. A data frame is fully loaded into the shift register 3 in n clock cycles, where n is the length of the shift register 3. A few more clock cycles are consumed in advancing the write control bit in the shift register 1. There may also be another write signal WR that is activated only after the data frame to be loaded into the shift register 3 and the write control bit in the write control shift register 1 are in place.
The data frame load and the write signal increment 4 continue until all the configuration bits are loaded into the device. The control circuitry for executing and synchronizing the data frame load and the write increment operation is not shown, though such circuitry is well known to those skilled in the art. Thus, according to the prior art, the total number of clock cycles needed to configure an FPGA/CPLD is greater than the total number of configuration latches in the given FPGA/CPLD.
In U.S. Pat. No. 5,995,988 to Freidin et al., serial loading of bits in groups has been described. Yet, this approach may require a relatively long time for loading.
An object of the present invention is to provide a programmable logic device in which a number of clock cycles required for configuration are reduced. In particular, this may be accomplished by presetting all the configuration latches to a predetermined state and then selectively changing states of specific configuration latches in the latch array.
This and other objects, features, and advantages of the present invention are provided by a system for the rapid configuration of a programmable logic device which may include first means or circuitry for selecting a logically continuous array of bits out of a total configuration map. Furthermore, second means or circuitry may also be included for selecting one or more of the bits in the selected arrays that are required to be toggled, as well as a third means or circuitry for changing the selected bits.
More particularly, the first means may include a write control shift register for selecting a row of the configuration memory of the programmable logic device. The second means may include a decoder for selecting one column at a time of the configuration memory of the programmable logic device. Further, the third means may include a pass transistor for connecting the input of a memory latch storing the bit to a logic 0 or logic 1 level.
Additionally, means or circuitry may be provided to generate the shift signal for the write control shift register (WCSR) by a combination of a defined output of the second means and a clock signal. For example, such means may include an AND gate, and the decoder may be a binary decoder. Further, multiple programmable logic devices may advantageously be enabled sequentially by a sequencing mechanism.
A counter may also be included for selecting the programmable logic device location. Additionally, the input to the decoder may be from a memory including the addresses of the locations of bits/bit clusters to be changed. The memory may include the values of only those locations that differ in the present configuration from the desired values in the new configuration to minimize memory size and configuration time. Also, the configuration memory may be programmed in multiple bits at a time using selection means and toggling means, in which the selection means may include decoders. Furthermore, the sequencing mechanism may include a daisy chain mechanism.